If those ops are register-register, how are they necessarily not-RISC?
Yes, division is inherently more complex than bitwise NAND, but it's not obvious to me where the line is that you find so clear.
FWIW, I've seen a very serious architecture proposal that used two instructions for memory-reads. (It had one instruction for memory writes.) Along those lines, register-value fetch can be moved into a separate instruction....
The sse1 instruction provide the option of register-register, but also support register-memory. I didn't realize it supported register-register mode, so now I see why it would be less obvious to you.
Why is copying a value from register to memory (or memory to register) "RISC" while performing some logical operation to the value to the value as moves "not risc"?
I'd agree that memory to memory is "not risc", but given the amount of work necessary to do a register access, it's unclear why doing work on a value is "not risc".
Datapaths are NOT the complex part of a microprocessor.
A very RISC chip usually just has ADD, OR, AND, LOAD, STORE, etc. But in x86 (CISC) we have things like these:
UNPCKLPS: (sse1) Unpack and Interleave Low Packed Single-FP Values
MOVSHDUP: (sse3) Move Packed Single-FP High and Duplicate
AAM: ASCII Adjust AX After Multiply