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If you assume that there is no cache (only on-die memory) and that memory is not shared between cores, things become much simpler and scale more linearly. Core-to-core communications and plenty of other details remain to spend man-years ironing out, but it seems like it would be possible to approach 64k cores or at least 16k.


Might be able to peel out the BCD stuff from the 6502 to free up a little additional space and approach communication between cores kinda like the "handshake bus" GreenArrays chips use: http://greenarraychips.com/home/documents/greg/PB003-100822-...




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