One difference between the standard cells in the article and the current ones is that the routing channels have been eliminated thanks to the many metal layers we now have. Back then we couldn't really afford to have metal cross the Vdd and ground lines at the top and bottom of the cells so we just stretched the polysilicon lines to the top and bottom edges. Routing was done by continuing the poly into the channel and then connecting cells with metal. This meant that though the decapped poly lines are just one thing in the photos, in terms of design the parts inside the cells are standard and the parts in the channel are custom.
This scheme works even with just poly and one level of metal, but if you have enough metal layers than you can run them through the cells themselves. You just have to avoid the vias that take the inputs and outputs down to the transistors. You have an additional gain if you flip every other row of cells so that the PMOS of two rows have the Vdd rail overlap and the NMOS of two rows have the ground rail overlap.
This scheme works even with just poly and one level of metal, but if you have enough metal layers than you can run them through the cells themselves. You just have to avoid the vias that take the inputs and outputs down to the transistors. You have an additional gain if you flip every other row of cells so that the PMOS of two rows have the Vdd rail overlap and the NMOS of two rows have the ground rail overlap.